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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]Re: [tlug] hardware
- Date: Tue, 20 May 2003 18:22:06 +0900 (JST)
- From: Tod McQuillin <devin@example.com>
- Subject: Re: [tlug] hardware
- References: <20030519195335.D64D.PETER@example.com> <200305191909.57155.jq@example.com><200305192302.56545@example.com> <200305201601.22120.jq@example.com>
On Tue, 20 May 2003, Jonathan Q wrote: > On Monday 19 May 2003 20:02, Sam Tilders wrote: > > > Is there a specific reason you condemn realtek? > > Realtek 8129 and 8139 chipsets have had a lot of problems, > particularly under load and more particularly if NFS is > involved. The driver code for one or more of the BSDs > described the level of brokenness in the the 81x9 chipsets > in fairly unflattering terms. Yes, there are some nice comments in there. Here's what Jonathan is referring to: /* * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is * probably the worst PCI ethernet controller ever made, with the possible * exception of the FEAST chip made by SMC. The 8139 supports bus-master * DMA, but it has a terrible interface that nullifies any performance * gains that bus-master DMA usually offers. * * For transmission, the chip offers a series of four TX descriptor * registers. Each transmit frame must be in a contiguous buffer, aligned * on a longword (32-bit) boundary. This means we almost always have to * do mbuf copies in order to transmit a frame, except in the unlikely * case where a) the packet fits into a single mbuf, and b) the packet * is 32-bit aligned within the mbuf's data area. The presence of only * four descriptor registers means that we can never have more than four * packets queued for transmission at any one time. * * Reception is not much better. The driver has to allocate a single large * buffer area (up to 64K in size) into which the chip will DMA received * frames. Because we don't know where within this region received packets * will begin or end, we have no choice but to copy data from the buffer * area into mbufs in order to pass the packets up to the higher protocol * levels. * * It's impossible given this rotten design to really achieve decent * performance at 100Mbps, unless you happen to have a 400Mhz PII or * some equally overmuscled CPU to drive it. [...] -- Tod McQuillin
- References:
- [tlug] hardware
- From: Peter Evans
- Re: [tlug] hardware
- From: Jonathan Q
- Re: [tlug] hardware
- From: Sam Tilders
- Re: [tlug] hardware
- From: Jonathan Q
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